Usually, a bottom-gate low-temperature polysilicon (LTPS) TFT includes a gate electrode, a gate insulation layer, a polysilicon semiconductor layer, a source electrode and a drain electrode. An amorphous silicon layer is formed at first, and then subjected to excimer laser annealing (ELA) treatment, so as to form the polysilicon semiconductor layer. The gate electrode is arranged under the gate insulation layer, and the gate insulation layer may include a protrusion at a position corresponding to the gate electrode. The flatness of the amorphous silicon layer may be adversely affected due to the protrusion, and during the ELA treatment, a crystallization effect may get worse. As a result, the resultant LTPS TFT may be provided with instable properties.